TY - JOUR
TI - An equivalent thermal conductivity model of through silicon via arrays for thermal analysis in 3-D integrated circuits
AU - Xu Zhao-Pei
AU - Wang Kang-Jia
JN - Thermal Science
PY - 2024
VL - 28
IS - 5
SP - 4081
EP - 4088
PT - Article
AB - As the CMOS technology continuously scales down into the deep submicron regime and approaches the physical limits of minimization, Moore's Law is hindered. The proposed 3-D integrated circuit technology based on through silicon via brings hope. Although 3-D integrated circuits bring many advantages over 2-D integrated circuits, the thermal management challenges still need to be addressed effectively. The through silicon via carry signals while facilitating the thermal transfer of stacked chips due to their high thermal conductivity and offer a potential thermal management solution for 3-D integrated circuits. The through silicon via are structured in arrays to significantly improve heat dissipation. This paper proposes a cellular array structure that offers better heat dissipation capabilities compared to conventional rectangular arrays. First, the through silicon via cellular arrangement is described. Secondly, a method for modelling the equivalent thermal conductivity of through silicon via arrays is proposed. Finally, the excellent performance of the cellular structure on thermal conductivity is verified by a comparative analysis of the thermal characteristics of the through silicon via array in the COM-SOL system using finite element method. The results presented in this paper are beneficial for designers to optimize the through silicon via array arrangement and predict the thermal performance of through silicon via arrays. In addition, it pro-vides a reference for 3-D integrated circuit reliability design.